Building a Developer Community for Quantum Error Correction with Riverlane’s Brierley
Quantum error correction (QEC) is the gating challenge to practical, utility-scale quantum computing—and the bottleneck is talent. In this focused talk, Steve Brierley (Founder & CEO, Riverlane) laid out why QEC is at an inflection point, what “real-time” error correction actually involves, and how to grow a global developer community with open tools that make hands-on QEC work accessible.
Why now: from theory to working systems
“Now is the time for quantum error correction.”
Brierley highlighted the field’s momentum over the last 12–18 months across multiple platforms:
Surface code below threshold: recent experiments demonstrated that adding more protection can lower logical error rates—evidence that QEC “actually works.”
Real-time decoding: Riverlane and Rigetti showed low-latency experiments with decoding in microseconds, a key building block toward fault tolerance.
Neutral-atom logic at scale: Harvard’s results showcased flexible layouts executing logic across large atomic arrays.
These results coincide with a surge in open-source QEC tools (e.g., simulators and decoders) and growing usage across the community—yet the talent pool is small. Brierley estimated ~400 people worldwide deeply understand QEC, even though “95%” of practitioners view it as the most important challenge. Closing that gap is now urgent.
Riverlane’s role: classical silicon for quantum reliability
Riverlane positions itself as a classical semiconductor company for quantum reliability—designing decoder chips and software that sit next to the quantum processor to keep pace with syndrome data and drive feedback:
2023: first decoder chip decoding at MHz rates to match QPU data streams.
2024: world’s first low-latency QEC experiments with Rigetti (microsecond-scale decoding).
2025: second-generation product made available to the broader ecosystem for real-time QEC integration with control stacks.
“We design the chips which—together with our software—solve real-time error correction.”
What real-time QEC entails (and why it’s hard)
Brierley broke down a typical QEC workflow into three iterative phases:
Design & simulate the QEC circuit
Choose codes and syndrome-extraction strategies; explore workarounds for imperfect qubits; prototype circuits using tools such as a Clifford simulator (he cited Stim). Output: a concrete QEC circuit mapped to the target device.Run the experiment with tight hardware coupling
Split the compiled description into:Control path: schedules pulses and native gates on the quantum device.
Decode path: configures the decoder with the expected parity checks and timing so it can interpret streaming measurements.
Achieving low latency requires extremely tight communication between the control system and decoder.
Analyze & iterate
Inspect IQ plots and logical error-rate behavior (looking for the hallmark decrease as protection increases). Build an error budget from correlation matrices; refine circuits, codes, and timings; repeat.
This end-to-end loop is still too hard for most teams to stand up quickly—which is exactly the barrier Riverlane is targeting with new open tools.
New tools for builders: DeltaKit + DeltaKit Textbook
To lower the on-ramp, Riverlane introduced DeltaKit (open source) and a companion DeltaKit Textbook:
End-to-end, modular toolkit to design, run, and analyze logical-level circuits on real hardware and simulators.
Realistic noise models to better predict hardware behavior and explain sim-vs-device gaps.
Building blocks for stability/memory experiments—and extensibility so teams can add their own components.
Developer experience focus so QEC teams can reproduce the Rigetti experiment flow and others without rebuilding infrastructure from scratch.
A soft launch at a recent QEC conference drew 100+ developer sign-ups, signaling pent-up demand for approachable, standards-leaning QEC tooling.
“We’re releasing DeltaKit… an end-to-end solution that allows you to run your first experiment in quantum error correction.”
Who should use this—and why it matters
Hardware companies: stand up reproducible QEC experiments faster; share internal methods with broader engineering teams.
HPC centers & national labs: evaluate QEC strategies at scale; integrate real-time decoding next to accelerators.
Universities & R1 departments: teach QEC with hands-on labs that reflect actual device workflows.
Industrial R&D teams: build internal know-how now so you’re ready to port applications to fault-tolerant hardware later.
The call to action
Upskill: invest in QEC literacy across teams—engineers, algorithm developers, and control-stack specialists.
Adopt open tools: use DeltaKit and similar projects to shorten time-to-experiment and share best practices.
Contribute: expand code libraries, noise models, and examples; report results so the community learns faster.
Bottom line: Fault tolerance won’t arrive by accident. It will be engineered—by a larger, better-equipped developer community working with shared tools and realistic workflows.